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The algorithm can be implemented in most FPGAs (vendor independent, doesn't rely on vendor specific resources)
Small area: 8.16 case 13% of a 100,000 gates device and less than 0.2% of a modern Virtex 4LX 200!
- 8.16 => 9.78 million/s
- 23 exact decimals => 5 million/s
Good speed vs area result, when more speed is needed we can use more cores in parallel (no special resources limits!)