/***********************************************************************

  Capsense example for Kefir I boards

  This file is part FPGA Libre project http://fpgalibre.sf.net/

  Description:
  This is a simple demo that polls the CapSense buttons and shows its
  status using the LEDs.
  Needs a 24 MHz oscillator, can be configured.

  To Do:
  -

  Author:
    - Salvador E. Tropea, salvador en inti.gob.ar

----------------------------------------------------------------------

 Copyright (c) 2016 Salvador E. Tropea <salvador en inti.gob.ar>
 Copyright (c) 2016 Instituto Nacional de Tecnología Industrial

 This file can be distributed under the terms of the GPL 2.0 license
 or newer.

----------------------------------------------------------------------

 Design unit:      Kefir_Capsense
 File name:        kefir_capsense.v
 Note:             None
 Limitations:      None known
 Errors:           None known
 Library:          None
 Dependencies:     None
 Target FPGA:      iCE40HX4K-TQ144                                    
 Language:         Verilog
 Wishbone:         None                                               
 Synthesis tools:  iCEcube2 2016.02
                   IceStorm/Yosys/Arachne-PNR
 Simulation tools: GHDL [Sokcho edition] (0.2x)
 Text editor:      SETEdit 0.5.x

************************************************************************/

`include "../verilog/capsense.v"
`include "../verilog/capsense_sys.v"

module Kefir_Capsense(
   input  CLK,
   inout  BTN1, BTN2, BTN3, BTN4,
   output LED1, LED2, LED3, LED4,
   output SS_B);

localparam DIRECT=1; // Direct status, else: toggle
localparam EXPLICIT_TBUF=1; // Manually instantiate tri-state buffers

assign SS_B=1; // Disable the SPI memory

wire capsense_oe;
wire [3:0] capsense_in;

CapSense_Sys #(.N(4), .DIRECT(DIRECT), .FREQUENCY(24)) CS
  (.clk_i(CLK), .rst_i(1'b0),
   .capsense_i(capsense_in),
   .capsense_oe(capsense_oe),
   .buttons_o({LED1,LED2,LED3,LED4}));

generate if (EXPLICIT_TBUF)
begin
  // Yosys doesn't support tri-states (11/2016), so we must instantiate the
  // pins manually.
  SB_IO #(
      .PIN_TYPE(6'b1010_01),
      .PULLUP(1'b0)
  ) buts [3:0] (
      .PACKAGE_PIN({BTN1,BTN2,BTN3,BTN4}),
      .OUTPUT_ENABLE(capsense_oe),
      .D_OUT_0(4'b0),
      .D_IN_0(capsense_in)
  );
end
else
begin
  assign {BTN1,BTN2,BTN3,BTN4}=capsense_oe ? 4'b0 : 4'bZ;
  assign capsense_in={BTN1,BTN2,BTN3,BTN4};
end endgenerate

endmodule