Introduction

• What is an FPGA?
• How the project was born?
• Goal and objectives
• Which devices and platforms?
• Components of the development cycle of FPGALibre
• HDL code
• Code edition
• Simulation
• Synthesis
• Hardware and transfer to FPGA

What is an FPGA?:

This project is oriented to people that already know what is an FPGA, therefore we will only say they are reconfigurable electronic circuits which allow creation of new circuits which behave as we wish. A better definition of the word FPGA can be found in the Wikipedia.

How the project was born?:

The FPGA Libre project (Free FPGA) was born with the idea of being able to share tools and cores developed in the Unidad Técnica Instrumentación y Control, (Instrumentation and Control Thecnical Unit) from the Electronics and Informatics center of INTI (Instituto Nacional de Tecnología Industrial) (National Institute of Industrial Technology, Argentine).

In the Primer Workshop Latinoamericano de Tecnología FPGA "First Latin American Workshop of FPGA Technology" we met a lot of people who want to share knowledge about FPGA and for that reason we decided to create this space as an open place for all those people who want to join us.

Goal and objectives:

The main goal of this project is to facilitate the exchange of elements necessary for project development with FPGAs.

The exchange of physical media (hardware) is complex due to the replication costs and exchange of software licensed under propietary models is usually a crime. For these reasons the project emphasize in free sofware, open source and in cores that can be redistributed under similar licenses.

Starting from these basis, the following formal objectives are enunciated:

1. To promote the development with FPGA devices using free software or open source tools.
2. To encourage the exchange and development of IP cores using licenses that hold the same spirit of free software.

Among all advantages of using free software we can mention:

• The ability to learn watching the source code of applications and cores.
• The possibility to freely adapt the code to special requirements of each one.
• The ability to improve the code and to offer those enhancements to all the community.
• Low cost. Proprietary products in this sector usually have high cost licenses or royalties. This limits and restrict their application in massive form for projects and institutions of low resources in developing countries.

Which devices and platforms?:

Our project is not bound to any device or platform in particular. But we are already using some for our projects.

At the present time the used platform is Debian GNU/Linux and FPGA devices are from Xilinx, but as it was already said the project is open.

Components of the development cycle of FPGALibre:

The component parts that make possible the development cycle with FPGA devices currently used by the developers of FPGA Libre can be summarized in the following items:

• HDL code
  • Selection of HDL language used for designs.
  • Code conventions and rules for group development and greater reusability
  • Cores interconnectivity.
  • HDL Extensions and helpers.
  • HDL libraries.
  • IP Cores.

• Code edition
  • Edition software.
  • Edition software helpers.

• Simulation
  • Simulation tool.
  • Test bench.
  • Test bench helpers.
  • Waveform visualization.
  • Simulation process helpers.

• Synthesis
  • Synthesis tool .

• Transfer to FPGA
  • FPGA device selection.
  • FPGA download configuration hardware.
  • FPGA download configuration software.

We will see these items in more detail.

HDL code:

Selection of HDL language used for designs

Several HDLs can be used to carry out the description of a design. The most used and popular are Verilog, VHDL and SystemC. Because VHDL is of common use in many university institutions and projects of great importance (for example the LEON processor) we believe it is the best alternative for the outlined objectives. For this reason the preferred language for the FPGA Libre project is VHDL, however it is open to any contribution or future advance in other languages.

The VHDL language is defined in the IEEE 1076 standard. Some very popular proprietary tools have implemented features that violate this standard.

Code rules and conventions for group development and greater reusability

The VHDL language, as many others, offer certain freedom in formating the code, indentation, name of variables, etc. However when you encourage group work to allow other people to collaborate and to increase the reusability of the code, it is necessary to define additional rules for code writing. For this topic we take two guidelines to write VHDL code: 1) The European Space Agency guidelines and 2) OpenCores project guidelines. Based on both, the FPGA Libre project defines its own guidelines for VHDL code writing.

To implement this concept it has been developed an extremly basic and simple lint for VHDL called bakalint. For further clarity on this concept, we mention a definition of lint taken from the web:

lint: "A Unix C language processor which carries out more thorough checks on the code than is usual with C compilers."

In this case the lint definition doesn't refer to C language but to VHDL. That is to say, a VHDL code parser that alert things the compiler accepts or ignores without complain. The objective is to have a tool that helps to apply the guidelines, achieving uniformity and coherence among different developers and projects.

cores Interconectivity

To take maximum advantage of IP cores and to achieve greater benefit from the modularity they offer, it is necessary to define and establish some common mechanism for interconnection. Following the project objectives, an open and free specification was searched to fulfill this requirement. Taking OpenCores as reference, the Wishbone interconnection architecture was selected for IPs in SoC. Besides their features and technical advantage, this specification is public domain and allows free utilization without any contract or royalty payment.

We use the WISHBONE Builder tool from OpenCores to automate the generation of intercon entities for Wishbone cores. The FPGA Libre project has carried out modifications and enhancements to this tool.

HDL extensions and helpers

VHDL language has several limitations compared with other programming languages like C. This fact dificult and delay application development. To solve some of these drawbacks, complementary tools were developed for this language. These are the developed tools at this time:

• vhdlspp - VHDL Simple Pre-Processor that allows to easily include files. Similar to the C language #include directive.
• hex2vhdl - File converter from HEX format to a VHDL array. Used, for example, to include the initial content of a processor program memory inside a design.
• xtracth - This is a very bare script to extract definitions from a VHDL package and to arrange them in a .h and/or a .inc file.

VHDL Libraries

Different libraries exist to facilitate and accelerate cores development. These are some of the utilized ones:

• std_logic_1164 - Basic handling of bits, standardized by IEEE
• numeric_std - Basic handling of integers, standardized by IEEE
• C - Emulation of the standard C library, ESNUG 2004

IP cores

There are great amount of IP cores available in the net, with licenses that allow their use without any type of constraints.

IP cores usage that don't follow the principles of free software, are discarded because they do not offer the source code, restrict its application field or request royalties payment.

From all the available IP cores with these licenses, this project prefers those writing in VHDL, which compile correctly with GHDL and has Wishbone interface.

Code edition:

Edition software

There are not a lot of free software text editors with advanced facilities for VHDL code edition. One of these editors is SETEdit, an editor thought for programmers with support for a great amount of programming languages. These are some of the features that make it a good choice to work with VHDL:

• Syntax highlight for VHDL.
• Specific macros for VHDL typical constructions.
• Usage of Exuberant CTAGS with specific support for VHDL.
• Indentation consistent with our project guidelines.

For more information see the SETEdit section.

Edition software helpers

There are external applications that can help in the edition work to enhance the capabilities of edition software. One of these applications is CTAGS or Exuberant CTAGS that helps in search and inspection tasks inside the source code. At the moment of writing this document the official version of Exuberant CTAGS supports Verilog but not VHDL. The FPGA Libre project has added support for VHDL in Exuberant CTAGS.

SETEdit can use Exuberant CTAGS to eases code navigation.

For more information consult the Exuberant CTAGS section.

Another useful tool is tpl2file which is an utility to extract templates from VHDL examples that come with ISE WebPack, and to arrange them in standalone files inside a directory hierarchy.

For more information consult the tpl2file section

Simulation:

Simulation tool

Thinking in core development in VHDL language applied mainly for FPGA devices, different alternatives have been evaluated. Always giving priority to free software or open source alternatives, we have evaluated the following simulation tools: SAVANT, FreeHDL, Alliance and GHDL. GHDL has been selected as main simulation tool due to their extended use and the capability of compiling without problems such projects as the LEON and the DLX processors. GHDL uses the GCC technology, the most used compiler in the free software community.

For more information consult the GHDL section.

Tests bench

To check the correct performance of a core, it is necessary to apply a stimulus to the core and to observe its behavior. VHDL language can also be used to carry out this task. Additional code that realizes this task is called testbench.

Test bench helpers

Many times writing of a simple testbench, where an input pattern correspond with an output pattern, can be tedious and monotonous. A tool called natebege has been created only for these simple cases. This tool automatically generates a testbench based on input and output patterns.

Other times, data generated by the testbench is of great volume and complex analysis. In these cases it becomes necessary to appeal to other software tools that process or analyze data generated by the testbench. Some options are programs in C language or Perl scripts, among others, that take data generated by testbench an then process it.

Waveforms visualization

Simulation programs can generate file dumps with all waveforms from simulation. Currently, in this the project, we work with the two formats supported by the GHDL:

• VCD Format: Verilog Change Dump or also Change Value Dump. This format originally disigned for Verilog, doesn't support the VHDL types.
• Specific format of the GHDL: GHDL Waveform Format.

The files in VCD format can be visualized with GTKWave and Dinotrace. The files in GHDL WF can only be visualized using a special version of GTKWave. Currently we are searching to improve GTKWave support for GHDL format and for types defined in VHDL std_logic.

For more data to consult the GTKWave section and the Dinotrace section.

Simulation process helpers

Generation of necessary files for simulation is a simple process that can become ugly when several description files and different assistance tools are used. To automate this type of tasks we use GNU Make.

Synthesis:

Synthesis tool

After the simulation process, we proceed to the synthesis stage of our design. Final results of synthesis are then transferred to the FPGA or to the configuration memory. Regrettably we don't know synthesis tools with free software or open source licenses. Two of the most important manufacturers of FPGA devices offers free use (freeware not free software) synthesis tools, each one for its own products.

At the beginnings of our work with FPGAs we have used devices from ALTERA company with MAX+PLUS software and also Quartus. This outlined two main problems: The utilization of Windows environments (because a freeware alternative doesn't exist for GNU/Linux operating systems) and the impossibility to automate the synthesis process with command line scripts without using the program IDE interface.

Because of these reasons and also taking into account that other workgroups with similar spirit have used Xilinx devices, we decided to stop the use of ALTERA devices. The FPGA Libre project is open to any technology and FPGA device, whenever its usage can be achieved under free software environments like GNU/Linux for example. The ISE WebPack synthesis tool from Xilinx is for free usage (you don't have to pay) but it is not free software (no source code available, no redistribution allowed). It has a native GNU/Linux version and it allows usage from command line. This facilitates automation of the whole development process with tools like GNU Make.

For more information see the ISE section.

Hardware and transfer to FPGA:

FPGA device selection

Due to utilization of ISE WebPack, our device selection was restricted to Xilinx devices. (Spartan II, Spartan 3/3A/3E, Spartan 6, Virtex 4/5/6).

Today we also include Lattice iCE40 devices.

Hardware development

To develop an application, besides the FPGA chip, it is necessary support electronics: printed circuits, supply circuits, memory, connectors, etc.

The easy way to start is buying some FPGA development kit (Board with FPGA). Our first development kit was a Memec Spartan II LC board.

After the initial stage of development, it is sometimes necessary to face the design, construction and assembling of an FPGA board. As part of our learning process, we planned to face the design of a board with features comparable to the development kit. Using only free software EDA tools and giving free access to documentation and design files.

We first developed S2Proto, and then we migrated to BGA technology and developed S3Proto-Mini.

Recently we developed a board using iCE40 devices: Kéfir I.

FPGA configuration hardware

FPGA devices have several mechanisms for programming its configuration. One of the mechanisms that assure hardware compatibility between different manufacturers and models is the IEEE 1149.1 standard from the JTAG (Joint Test Action Group). Hardware interface for JTAG programming may be useful for more than one FPGA or configuration memory manufacturer.

Based on different application notes from Xilinx and from circuits published on the web, we have developed a very low cost JTAG parallel port interface. The circuit was developed with a free software EDA tool called KiCad. All design files and associate documentation are available and free for any use.

For more data: DLC5

The problem is that parallel ports are obsolete now, and hence you need an adaptor. So we migrated to USB and developed a versatile cable based on the FT2232H chip: MILK.

FPGA configuration (transferring) software

Transferring configuration to hardware involves two types of knowledge. Firts, the transferring protocol, JTAG in our case, and second the knowledge of specific features of the used device.

The Xilinx Impact tool solves both aspects but has a very important drawback. Its GNU/Linux version requires the use of a special distribution (Red Hat Enterpise) and proprietary kernel modules. However, Michael Gernoth created a nice dynamic library to enable its use without the need of such kernel modules.

Using the above mentioned library and a set of Perl Scripts you can transfer the configuration in a simple and automated way. These tools can be found in the iMPACT Helper package.