FPGA Libre
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We don't have an english translation of the whole site. We are looking for volunteers for such a task.

Here we will maintain a small list of resources generated by the project. Some resources are just adaptations or enhancements of already existing projects others born from this project. In most cases the resources have its user interface in english.

Text editor:

Text editor with advanced features to edit VHDL sources: SETEdit. Sources, sources for support library, SETEdit v0.5.8 (Jessie AMD64) and Turbo Vision 2.2.1-4 (Jessie AMD64)

VHDL Tags:

Exuberant CTAGS v5.5.4 with VHDL support: Sources and binaries for Debian and similar OSs.


ISE WebPack 6/7 templates extractor: tpl2file. (Perl script, run it on the data directory of ISE WebPack.


VHDL simulator: GHDL. GHDL 0.20 official release in .deb. GHDL 0.19 official release in .deb.

GHDL examples:

Examples showing how to use GHDL (also GTKWave and bakalint) Ejemplos para GHDL.

Waveforms viewer (GTKWave):

GTKWave waveform viewer with VHDL and GHW (GHDL 0.19+ format) support: binaries for Debian and similar OSs GTKWave.

Waveforms viewer (Dinotrace):

Dinotrace waveform viewer: Dinotrace 9.3a (Debian)

Schematic and PCB:

Schematic and PCB tool: KiCad. Debian packages (Sarge):

KICAD tools:

Testbench generator:

natebege (Naive Test Bench Generator): Sources (natebege) and Debian package (natebege)

Coding guidelines:

Coding guidelines for our project: guidelines (Spanish only! but you can look at the VHDL examples)


Lint tool for the above mentioned guidelines: bakalint

JTAG cable:

Schematic and PCB for the Xilinx's Parallel III (DLC5) JTAG cable: DLC5 (KiCad format)

Interconnection Bus:

Wishbone Spec B.3: Wishbone (SoC interconnection/bus)

Wishbone Builder:

Wishbone Builder, INTERCON generator: WISHBONE Builder

VHDL Simple Preprocessor:

Tool to "#include" code in VHDL: vhdlspp (Debian: vhdlspp)

Hex to VHDL:

Tool to convert PIC's .hex files to VHDL code: hex2vhdl (Debian: hex2vhdl)

C for VHDL:

VHDL library to emulate C standard library: C (adapted for GHDL - original version)

iMPACT Helper:

Wrapper to run Xilinx iMPACT without installing the kernel modules. It also includes some useful Perl scripts to make easier the configuration job. Tarball: iMPACT Helper v0.8.0 (Src) (Debian: iMPACT Helper v0.8.0 (AMD64)).

Synthesis report:

A Perl script to extract information from synthesis reports. Tarball: ResumenXil (Debian: ResumenXil).

ISE example:

ISE command line usage example: ISE examples Needs: ResumenXil and iMPACT Helper.

Avnet S3A Eval Kit:

Tool to program the Avnet Spartan 3A Eval Kit (replaces the Window's AvProg tool on Linux systems). Sources: ASTriAEKiPro 1.2.2 Debian GNU/Linux: ASTriAEKiPro 1.2.2 (AMD64)

JTAG tool (xilinx_jtag):

Program to download the bitstream to a Virtex or Spartan FPGA using JTAG (Linux only): Sources xilinx-jtag Debian @xilinx_jtag_deb.

JTAG tool (JBit):

Programs to download the bitstream to a XC18V01 PROM or a XC2S100 FPGA (Can be configured for other devices. You have to download both. Various cables supported): Sources bit2svf and jtag. Debian bit2svf y jtag.

CVS Helpers:

A set of scripts to help using CVS, they include:

  • cvs-bkp Creates a tarball containing all the files for a project. Just running it at the root of a CVS project and you'll get tarball named ../PROJECT-DATE.tar.bz2
  • cvs-create Used to add a new module (project) to the CVS repository.
  • cvs-diff Is an easy way to create a diff between the working copy and the current CVS content. It does an update first.
  • cvs-oo-helper Allows the use of Open Document files (OASIS, ODx - i.e created using Open Office) with CVS. They are stored uncompressed and you can share images with other documents.
  • cvs-putlog Adds a change log to a VHDL file.
  • cvs-update Equivalent to "cvs -z3 update -dP", filters the "cvs update: Updating *" messages and calls cvs-oo-helper to keep the Open Document files synchronized.

Tarball: CVS Helpers 2.4.1 (Debian: CVS Helpers 2.4.1)


S3PROTO-MINI is a simple FPGA development board released under a free hardware license. It has a Xilinx Spartan 3E device (XC3S1600E) with a BGA 320 Package. Power is provided by the S3-Power modele, also under a free hardware license.

Full design information: http://sourceforge.net/projects/fpgalibre/files/S3Proto-Mini/

Solder side


Various links to related tools (headers in spanish, descriptions in english).

tpl2file SETEdit SETEdit ectags GNU/Make hex2vhdl vhdlspp natebege GHDL bakalint GHDL GTKWave Dinotrace GCC Perl ISE iMPACT Helper ASTriAEKiPro :-? :'-( (:-& %-) SETEdit Seppuku Simplified Cycle


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